High-level integrated circuit (IC) description languages such as VHDL and Verilog® are commonly used to design circuits. One embodiment of VHDL is described in greater detail in “IEEE Standard VHDL Language Reference Manual,” ANSI Std. 1076–1993, published Jun. 6, 1994. One embodiment of Verilog® is described in greater detail in “IEEE Standard Hardware Description Language Based on the Verilog® Hardware Description Language,” IEEE Standard 1364–1995, published Oct. 14, 1996. These high-level IC description languages allow a circuit designer to design and simulate circuits by using high-level code to describe the structure and/or behavior of the circuit being designed.
The high-level IC description language code is used to produce a netlist that describes an interconnection of circuit components to provide desired functionality. The netlist can then be used to develop the layout and ultimately fabricate an IC having the functionality of the designed circuit. The netlist can also be used for verification purposes.
Over time, many complex circuits have been designed using high-level IC description languages. The complexity of the code describing the circuits increases with the complexity of the circuit described, which in turn increases the cost of modifications to customize the circuit for new environments especially if the code is poorly documented and/or the original circuit designer is not available.
One component of a circuit design that is often modified to adapt the circuit design to a new environment is the state machine. A state machine is often used for control purposes, which is dependent on the environment in which the circuit design must operate. Therefore, in order to modify the circuit design to operate in a new environment, the state machine is often modified accordingly.
What is needed is a tool for recognizing and extracting state machines from high-level IC description language code.